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Q. No.When a \(\mathrm{p\text-n}\) junction is formed, the atoms on the \(\mathrm p\)-side are:
| 1. | neutral | 2. | slightly positive |
| 3. | slightly negative | 4. | all negative |
Subtopic: PN junction |
Level 4: Below 35%
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When light of a sufficiently high frequency falls on a photodiode:
| 1. | its resistance increases |
| 2. | its resistance decreases |
| 3. | it generates a forward EMF |
| 4. | it generates a back-EMF |
Subtopic: Applications of PN junction |
Level 4: Below 35%
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In the circuit shown, \(5~\text{V}\) represents TRUE (binary \(1\)) and \(0~\text V\) represents FALSE (binary \(0\)). The diodes are ideal. \(A,B,C\) are the inputs and \(Y\) the output. What logic does the circuit represent?
| 1. | AND \((A,B,C)\) | 2. | OR \((A,B,C)\) |
| 3. | NOT \(\bigg(\text{AND }(A,B,C)\bigg)\) | 4. | NOT \(\bigg(\text{OR }(A,B,C)\bigg)\) |
Subtopic: Logic gates |
Level 4: Below 35%
Hints
The peak voltage in the output of a half-wave rectifier is \(30 ~\text{V}.\) The RMS voltage of the output wave is: (assuming no distortion in wave)
| 1. | \(\dfrac{30}{\sqrt2}~\text{V}\) | 2. | \(15 ~\text{V}\) |
| 3. | \(\dfrac{15}{\sqrt2}~\text{V}\) | 4. | \(10 ~\text{V}\) |
Subtopic: Rectifier |
Level 3: 35%-60%
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The circuit shown in figure is given an input signal \(V_i,\) which varies with time and the corresponding output is \(V_o.\) Then,
| 1. | \(V_o=V_i+E\) |
| 2. | \(V_o=V_i-E\) |
| 3. | \(V_o=V_i,\) only when \(V_i>E\) |
| 4. | \(V_o=V_i,\) only when \(V_i<E\) |
Subtopic: PN junction |
Level 3: 35%-60%
Hints
If an AND-gate and an OR-gate are OR-ed together, the resulting gate is:
1. AND
2. OR
3. XOR
4. none of the above
1. AND
2. OR
3. XOR
4. none of the above
Subtopic: Logic gates |
Level 3: 35%-60%
Hints
The input to a Zener diode circuit is an AC-voltage along with a DC: \(V_i=(20~\text V)\sin\omega t+(20~\text V)~\)
Current flows through the diode:
Current flows through the diode:
| 1. | continuously, in both directions |
| 2. | continuously, only in one direction |
| 3. | intermittently, in both directions |
| 4. | intermittently, only in one direction |
Subtopic: Applications of PN junction |
Level 3: 35%-60%
Hints
The output \((Y)\) of the digital logic circuit shown in the diagram is:
| 1. | \(A~\text{AND}~B~\text{AND}~C\) | 2. | \((A~\text{AND}~B)~\text{OR}~C\) |
| 3. | \(B~\text{OR}~C\) | 4. | none of these |
Subtopic: Logic gates |
Level 3: 35%-60%
Hints
The voltage \(V_{AB}=20~\text{V}\) at its peak value, and is sinusoidal in time. The current \(i\) (in amperes), when plotted as a function of time, is given by:
(consider the diodes as ideal.)
(consider the diodes as ideal.)
| 1. |  |
2. |  |
| 3. |  |
4. |  |
Subtopic: PN junction |
Level 3: 35%-60%
Hints
A voltage \(V_{AB}\) is applied to the left side input and the potential differences \(V_{AX}\) and \(V_{XY}\) are measured. Assume the diodes are ideal i.e., there is no potential difference across the diodes in forward bias. Which of the following is true?
1. \(\text{If}~V_{AB}>0, V_{AX}>0\)
2. \(\text{If}~V_{AB}>0, V_{XY}>0\)
3. \(\text{If}~V_{AB}<0, V_{XY}>0\)
4. \(\text{If}~V_{AB}<0, V_{AX}>0\)
1. \(\text{If}~V_{AB}>0, V_{AX}>0\)
2. \(\text{If}~V_{AB}>0, V_{XY}>0\)
3. \(\text{If}~V_{AB}<0, V_{XY}>0\)
4. \(\text{If}~V_{AB}<0, V_{AX}>0\)
Subtopic: PN junction |
Level 3: 35%-60%
Hints
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