| 1. | \(\dfrac{30}{\sqrt2}~\text{V}\) | 2. | \(15 ~\text{V}\) |
| 3. | \(\dfrac{15}{\sqrt2}~\text{V}\) | 4. | \(10 ~\text{V}\) |
| 1. | metals |
| 2. | intrinsic semiconductors |
| 3. | \(\mathrm{p} \text-\)type extrinsic semiconductors |
| 4. | \(\mathrm{n} \text-\)type extrinsic semiconductors |
| 1. | \(\dfrac{1}{7}\) A | 2. | \(\dfrac{1}{6}\) A |
| 3. | \(\dfrac{1}{25}\) A | 4. | \(\dfrac{1}{180}\) A |
| 1. | \(100~\Omega\) if \(V_A>V_B\) and \(200~\Omega\) if \(V_A<V_B\) |
| 2. | \(100~\Omega\) if \(V_A<V_B\) and \(200~\Omega\) if \(V_A>V_B\) |
| 3. | \(100~\Omega\) |
| 4. | \(200~\Omega\) |
| 1. | \(120\) Hz | 2. | zero |
| 3. | \(30\) Hz | 4. | \(60\) Hz |
| 1. | decreases for conductors but increases for semiconductors. |
| 2. | increases for both conductors and semiconductors. |
| 3. | decreases for both conductors and semiconductors. |
| 4. | increases for conductors but decreases for semiconductors. |
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The output of the logic circuit shown is equivalent to a/an:
1. \(\text{OR}\) gate
2. \(\text{NOR}\) gate
3. \(\text{AND}\) gate
4. \(\text{NAND}\) gate
The circuit represents a full wave bridge rectifier when switch \(S\) is open. The output voltage \((\text V_0)\) pattern across \(R_L\) when \(S\) is closed:
| 1. | |
2. | |
| 3. | 4. |
| Assertion (A): | The value of current through \(\mathrm{p\text-n}\) junction in the given figure will be \(10~\text{mA}.\) |
| Reason (R): | In the above figure, \(\mathrm{p\text-}\)side is at a higher potential than \(\mathrm{n\text-}\)side. |
| 1. | Both (A) and (R) are True and (R) is the correct explanation of (A). |
| 2. | Both (A) and (R) are True but (R) is not the correct explanation of (A). |
| 3. | (A) is True but (R) is False. |
| 4. | Both (A) and (R) are False. |