\(A\) | \(B\) | \(Y\) |
0 0 1 1 |
0 1 0 1 |
1 0 1 0 |
1. | \(\text{NOR}\) gate | 2. | \(\text{OR}\) gate |
3. | \(\text{AND}\) gate | 4. | \(\text{NAND}\) gate |
1. | \(A=1,B=1,Y=1\) |
2. | \(A=0,B=1,Y=1\) |
3. | \(A=1,B=0,Y=0\) |
4. | \(A=0,B=0,Y=1\) |
1. | \(A\cdot B\) | 2. | \(\overline{A}\cdot\overline{B}\) |
3. | \(A+B\) | 4. | \(\overline{A}+\overline{B}\) |
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The output of the logic circuit shown is equivalent to a/an:
1. \(\text{OR}\) gate
2. \(\text{NOR}\) gate
3. \(\text{AND}\) gate
4. \(\text{NAND}\) gate