Two ideal diodes are connected to a battery as shown in the circuit. The current supplied by the battery is:

1. \(0.75~\text{A}\) 2. zero
3. \(0.25~\text{A}\) 4. \(0.5~\text{A}\)

Subtopic:  PN junction |
 88%
Level 1: 80%+
AIPMT - 2012
Hints

In a CE transistor amplifier, the audio signal voltage across the resistance of 2 kΩ is 2V. If the base resistance is 1 kΩ and the current amplification of the transistor is 100, the input signal voltage is:

1. 0.1 V

2. 1.0 V

3. 1 mV

4. 10 mV

 72%
Level 2: 60%+
AIPMT - 2012
Hints

\(\mathrm{C}\) and \(\mathrm{Si}\) both have the same lattice structure, having \(4\) bonding electrons in each. However, \(\mathrm{C}\) is an insulator whereas \(\mathrm{Si}\) is an intrinsic semiconductor. This is because:
1. in the case of \(\mathrm{C},\) the valence band is not completely filled at absolute zero temperature.
2. in the case of \(\mathrm{C},\) the conduction band is partly filled even at absolute zero temperature.
3. the four bonding electrons in the case of \(\mathrm{C}\) lie in the second orbit, whereas in the case of \(\mathrm{Si},\) they lie in the third.
4. the four bonding electrons in the case of \(\mathrm{C}\) lie in the third orbit, whereas for \(\mathrm{Si},\) they lie in the fourth orbit.
Subtopic:  Energy Band theory |
 72%
Level 2: 60%+
NEET - 2012
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Transfer characteristics [output voltage (Vo) vs input voltage (Vi)] for a base biased transistor in CE configurations are as shown in the figure. For using the transistor as a switch, it is used:

1. In region III

2. Both in the region (I) and (III)

3. In region II

4. In region I

 78%
Level 2: 60%+
AIPMT - 2012
Hints

The figure shows a logic circuit with two inputs \(A\) and \(B\) and the output \(C\). The voltage waveforms across \(A\), \(B\), and \(C\) are as given. The logic circuit gate is:
         

1. \(\text{OR}\) gate
2. \(\text{NOR}\) gate
3. \(\text{AND}\) gate
4. \(\text{NAND}\) gate

Subtopic:  Logic gates |
 85%
Level 1: 80%+
AIPMT - 2012
Hints

The symbolic representation of four gates is shown as: 
   
Pick out which ones are for AND, NAND, and NOT gates, respectively.

1.  (i), (iv), and (iii)

2.  (ii), (iii), and (iv)

3.  (ii), (iv), and (iii)

4.  (ii), (iv), and (i)

Subtopic:  Logic gates |
 89%
Level 1: 80%+
AIPMT - 2011
Hints

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If a small amount of antimony is added to germanium crystal:
 
1. the antimony becomes an acceptor atom
2. there will be more free electrons than holes in the semiconductor
3. its resistance is increased
4. it becomes a \(p\small{-}\)type semiconductor

Subtopic:  Types of Semiconductors |
 83%
Level 1: 80%+
AIPMT - 2011
Hints

In a forward biasing of the p-n junction:
 
1. the positive terminal of the battery is connected to the p-side and the depletion region becomes thick.
2. the negative terminal of the battery is connected to the n-side and the depletion region becomes thin.
3. the positive terminal of the battery is connected to the n-side and the depletion region becomes thin.
4. the negative terminal of the battery is connected to the p-side and the depletion region becomes thick.

Subtopic:  PN junction |
 76%
Level 2: 60%+
AIPMT - 2011
Hints

A transistor is operated in a common emitter configuration at Vc =2 V such that a change in the base current from 100 μA to 300 μA produces a change in the collector current from 10 mA to 20mA. The current gain is:

1.  75

2.  100 

3.  25

4.  50

 75%
Level 2: 60%+
AIPMT - 2011
Hints

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Which one of the following statements is false?

1. Pure Si doped with trivalent impurities gives a p-type
semiconductor.
2. The majority of carriers in an n-type semiconductor are holes.
3. The minority carriers in a p-type semiconductor are electrons.
4. The resistance of intrinsic semiconductors decreases with an
increase in temperature.

Subtopic:  Types of Semiconductors |
 87%
Level 1: 80%+
AIPMT - 2010
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