7.5 AC Voltage Applied to a Capacitor

 Figure 7.8 shows an ac source ε generating ac voltage v = v_msinωt connected to a capacitor only, a purely capacitive ac circuit.

When a capacitor is connected to a voltage source in a dc circuit, current will flow for the short time required to charge the capacitor. As charge accumulates on the capacitor plates, the voltage across them increases, opposing the current. That is, a capacitor in a dc circuit will limit or oppose the current as it charges. When the capacitor is fully charged, the current in the circuit falls to zero.

When the capacitor is connected to an ac source, as in Fig. 7.8, it limits or regulates the current, but does not completely prevent the flow of charge. The capacitor is alternately charged and discharged as the current reverses each half cycle. Let q be the charge on the capacitor at any time t. The instantaneous voltage v across the capacitor is

(7.15)

From the Kirchhoff’s loop rule, the voltage across the source and the capacitor are equal,

To find the current, we use the relation

Using the relation, $\cos \omega t=\sin \left(\omega t+\frac{\pi }{2}\right)$, we have

$i=i_m\sin \left(\omega t+\frac{\pi }{2}\right)$(7.16)

where the amplitude of the oscillating current is i_m = (ωC)v_m. We can rewrite it as

Comparing it to i_m= v_m/R for a purely resistive circuit,  we find that (1/ωC) plays the role of resistance. It is called capacitive reactance and is denoted by X_c,

X_c= 1/ωC (7.17)

so that the amplitude of the current is

(7.18)

The dimension of capacitive reactance is the same as that of resistance and its SI unit is ohm (Ω). The capacitive reactance limits the amplitude of the current in a purely capacitive circuit in the same way as the resistance limits the current in a purely resistive circuit. But it is inversely proportional to the frequency and the capacitance.

A comparison of Eq. (7.16) with the equation of source voltage, Eq. (7.1) shows that the current is π/2 ahead of voltage.

Figure 7.9 (a) A Phasor diagram for the circuit in Fig. 7.8. (b) Graph of v and i versus ωt.

Figure 7.9(a) shows the phasor diagram at an instant t₁. Here the current phasor I is π/2 ahead of the voltage phasor V as they rotate counterclockwise. Figure 7.9(b) shows the variation of voltage and current with time. We see that the current reaches its maximum value earlier than the voltage by one-fourth of a period.

The instantaneous power supplied to the capacitor is

p_c = i v = i_m cos(ωt)v_m sin(ωt)

            = i_m v_m cos(ωt) sin(ωt)

(7.19)

So, as in the case of an inductor, the average power

since ωt)> = 0 over a complete cycle. Figure 7.10 explains it in detail.

Thus, we see that in the case of an inductor, the current lags the voltage by π/2 and in the case of a capacitor, the current leads the voltage by π/2.

                           One complete cycle of voltage/current. Note that the current leads the voltage.

 

 

0-1 The current i flows as shown and from the maximum at 0, reaches a zero value at 1. The plate A is charged to positive polarity while negative charge q builds up in B reaching a maximum at 1 until the current becomes zero. The voltage vc = q/C is in phase with q and reaches maximum value at 1. Current and voltage are both positive. So p = vci is positive.

Energy is absorbed from THE SOURCE during this quarter cycle AS THE CAPACITOR IS CHARGED.

1-2 The current i reverses its direction. The accumulated charge is depleted i.e., the capacitor is discharged during this quarter cycle.The voltage gets reduced but is still positive. The current is negative. Their product, the power is negative.

the Energy absorbed during THE 1/4 CYCLE 0-1 IS RETURNED DURING this QUARTER.

 

2-3 As i continues to flow from A to B, the capacitor is charged to reversed polarity i.e., the plate B acquires positive and A acquires negative charge. Both the current and the voltage are negative. Their product p is positive. The capacitor ABSORBS ENERGY during this 1/4 cycle.

 

3-4 The current i reverses its direction at 3 and flows from B to A. The accumulated charge is depleted and the magnitude of the voltage vc is reduced. vc becomes zero at 4 when the capacitor is fully discharged. The power is negative.ENERGY ABSORBED DURING 2-3 IS RETURNED TO THE SOURCE. NET ENERGY ABSORBED IS ZERO.

Figure 7.10 Charging and discharging of a capacitor.