The output of the OR gate is 1:

1. only if both inputs are zero.

2. if either or both inputs are 1.

3. only if both inputs are 1.

4. if any of the inputs is zero.

In the circuit shown, $I_1 and I_2$ are respectively:
(If diodes are ideal)

1. 0, 0

2. 5 mA, 5 mA

3. 5 mA, 0

4. 0, 5 mA

The LED:

1. is reverse-biased.

2. is forward-biased.

3. can be made of GaAs.

4. both (2) & (3) are correct.

Logic gates X and Y have the truth tables shown below:

When the output of X is connected to the input of Y, the resulting combination is equivalent to a single:

1. NOT gate

2. OR gate

3. NAND gate

4. AND gate

The output in the circuit shown in the figure taken across a capacitor is:

1.		2.
3.		4.

The depletion layer in the P–N junction region is caused by:

In the given circuit, PN-junction diodes ${\mathrm{D}}_1,$ ${\mathrm{D}}_2,$ $\mathrm{and}$ ${\mathrm{D}}_3$ are ideal. For the following potential of A and B, the correct increasing order of resistance between A and B will be:

i.  –10V, –5V
ii.  –5V, –10V
iii.  –4V, –12V

1. (i) < (ii) < (iii)
2. (iii) < (ii) < (i)
3. (ii) = (iii) < (i)
4. (i) = (iii) < (ii)

The combination of gates shown below is equivalent to:
                
1. AND gate

2. XOR gate

3. NOR gate

4. NAND gate

Current $I_1$ through the Zener diode shown in the circuit is:
      
1. Zero
2. 0.6 mA
3. 0.2 mA
4. 0.8 mA

In the given circuit, the power developed in 2 k$\Omega$ resistor is:

1. 36 mW

2. 12 mW

3. 144 mW

4. 72 mW