1. | \(D_1\) and \(D_2\) both are forward biased |
2. | \(D_1\) and \(D_2\) both are reverse biased |
3. | \(D_1\) is forward biased, \(D_2\) is reverse biased |
4. | \(D_1\) is reverse biased, \(D_2\) is forward biased |
1. | \(120\) Hz | 2. | zero |
3. | \(30\) Hz | 4. | \(60\) Hz |
The circuit represents a full wave bridge rectifier when switch \(S\) is open. The output voltage \((\text V_0)\) pattern across \(R_L\) when \(S\) is closed:
1. | |
2. | |
3. | 4. |