The truth table for the circuit given in the fig. is:
           

 
1. \(A\) \(B\) \(Y\) 2. \(A\) \(B\) \(Y\)
0 0 1 0 0 1
0 1 1 0 1 1
1 0 1 1 0 0
1 1 1 1 1 0
3. \(A\) \(B\) \(Y\) 4. \(A\) \(B\) \(Y\)
0 0 0 0 0 1
0 1 0 0 1 0
1 0 1 1 0 0
1 1 1 1 1 0

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The logic gate equivalent to the given logic circuit is:

                

1. AND
2. OR
3. NOR
4. NAND

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In the digital logic circuit shown, what is the sequence of output values at terminal \(Z\) corresponding to the input combinations \((A,B)=(1,0),(0,0),(1,1)\) and \((0,1)\text{?}\)

       

1. \(1,0,1,1\)
2. \(0,1,0,0\)
3. \(0,0,1,0\)
4. \(1,1,0,1\)

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A diode with a forward bias voltage drop of \(0.5~\text{V}\) has a maximum safe current rating of \(10~\text{mA}.\) Suppose this diode is connected in series with a resistor to a battery of EMF \(1.5~\text{V}.\)What minimum resistance value is required to ensure the current does not exceed the diode's safe operating limit?
1. \(300~\Omega \)
2. \(50~\Omega \)
3. \(100~\Omega \)
4. \(200~\Omega\)

Subtopic: Β PN junction |
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If a semiconductor photodiode can detect a photon with a maximum wavelength of \(400~\text{nm},\) then the energy of its band gap is:
(take Planck’s constant \(h=6.63 \times 10^{-34} \text { J-s }\) and speed of light \(c=3 \times 10^8\) m/s)
1. \(3.1~\text{eV}\)
2. \(1.1~\text{eV}\)
3. \(2.0~\text{eV}\)
4. \(1.5~\text{eV}\)

Subtopic: Β Applications of PN junction |
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With increasing biasing voltage of a photodiode, the photocurrent magnitude:

1. increases initially and saturates finally.
2. increases initially and after attaining certain value, it decreases.
3. increases linearly.
4. remains constant.

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Two Zener diodes (\(A\) and \(B\)) having breakdown voltages of \(6~\text{V}\) and \(4~\text{V}\) respectively, are connected as shown in the circuit below. The output voltage \(V_0\) variation with input voltage linearly increasing with time, is given by: (\(V_{\text{input}}=0~\text{volt}\) at \(t=0~\text{second}\) and figures are qualitative)

 

1.  
2.  
3.  
4.  
Subtopic: Β Applications of PN junction |
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Take the breakdown voltage of the Zener diode used in the given circuit as \(6~\text{V}\). For the input voltage shown in figure below, the time variation of the output voltage is: (Graphs drawn are schematic and not to scale)

 

1. 2.
3. 4.
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For extrinsic semiconductors, when doping level is increased:

1. Fermi-level of \(p\)-type semiconductors will go upward and Fermi-level of \(n\)-type semiconductors will go downward.
2. Fermi-level of \(p\)-type semiconductors will go downward and Fermi-level of \(n\)-type semiconductors will go upward.
3. Fermi-level of both \(p\)-type and \(n\)-type semiconductors will go upward for \(T>T_F\) K and downward for \(T<T_F\) K, where \(T_F\) is Fermi temperature.
4. Fermi-level of \(p\) and \(n\)-type semiconductors will not be affected.

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The truth table for the following logic circuit is :

 

1. A B Y    2. A B Y
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
3. A B Y 4. A B Y
0 0 1 0 0 0
0 1 0 0 1 1
1 0 1 1 0 0
1 1 0 1 1 1
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