In NPN transistor the collector current is 10 mA. If 90% of electrons emitted reach the collector, then

(1) Emitter current will be 9 mA

(2) Emitter current will be 11.1 mA

(3) Base current will be 0.1 mA

(4) Base current will be 0.01 mA

Subtopic:  Transistor (OLD NCERT) |
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In a transistor in CE configuration, the ratio of power gain to voltage gain is 
(1) α                                     

(2) β/α 

(3) βα                                     

(4) β 

Subtopic:  Transistor (OLD NCERT) |
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Given below are symbols for some logic gates

The XOR gate and NOR gate respectively are 
(a) 1 and 2                  (b) 2 and 3
(c) 3 and 4                  (d) 1 and 4

Subtopic:  Logic gates |
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Given below are four logic gate symbol (figure). Those for OR, NOR and NAND are respectively 

(a) 1, 4, 3                     (b) 4, 1, 2
(c) 1, 3, 4                     (d) 4, 2, 1

Subtopic:  Logic gates |
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The following truth table corresponds to the logic gate

A  0  0  1  1
B  0  1  0  1
X  0  1  1  1

(1) NAND                     

(2) OR

(3) AND                       

(4) XOR

Subtopic:  Logic gates |
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The combination of ‘NAND’ gates shown here under (figure) are equivalent to

1. An OR gate and an AND gate respectively
2. An AND gate and a NOT gate respectively
3. An AND gate and an OR gate respectively
4. An OR gate and a NOT gate respectively.

Subtopic:  Logic gates |
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A truth table is given below. Which of the following has this type of truth table 

A  0  1  0  1
B  0  0  1  1
y  1  0  0  0

(1) XOR gate

(2) NOR gate

(3) AND gate

(4) OR gate

Subtopic:  Logic gates |
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For the given combination of gates, if the logic states of inputs A, B, C are as follows A = B = C = 0 and A = B = 1, C = 0 then the logic states of output D are

(1) 0, 0

(2) 0, 1

(3) 1, 0

(4) 1, 1

Subtopic:  Logic gates |
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Boolean algebra is essentially based on 

(1) Truth

(2) Logic

(3) Symbol

(4) Numbers

Subtopic:  Logic gates |
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 The logic behind the ‘NOR’ gate is that it gives

(1) High output when both the inputs are low

(2) Low output when both the inputs are low

(3) High output when both the inputs are high

(4) None of these

Subtopic:  Logic gates |
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